The trend in semiconductor technology to double the functional complexity of its products every 18 months (Moore's “law”), which is still valid today after having dominated the industry for the last three decades, has several implicit consequences. First, the cost per functional unit should drop with each generation of complexity so that the cost of the product with its doubled functionality would increase only slightly. Second, the higher product complexity should largely be achieved by shrinking the feature sizes of the chip components while holding the package dimensions constant; preferably, even the packages should shrink. Third, the increased functional complexity should be paralleled by an equivalent increase in reliability of the product. And fourth, but not least, the best financial profit rewards were held out for the ones who were ahead in the marketplace in reaching the complexity goal together with offering the most flexible products for application.
One area of integrated circuit manufacturing technology that poses difficulties in continued miniaturization and cost reduction is that of making electrical contact to a transistor device. The manufacturing process utilizes multiple patterning levels that require aligning a photolithographic mask with lower levels in the fabrication sequence. In the case of MOS transistors, conventional manufacturing practice requires aligning the vertical conductors that make contact with the transistor (appropriately referred to as “contacts”) with the source and drain regions of the transistor. Conventional MOS transistors use a spacer on the gate electrode sidewall. Because of alignment tolerances, space must be designed between the sidewall spacer and the contact so that when maximum misalignment occurs, the contact does not hit the sidewall spacer. When the contact does hit the spacer, the area of electrically conductive contact to the substrate is reduced, leading to increased resistance of the contact and resulting yield fallout. Thus, there are competing factors to be balanced by the manufacturer: maximum density of transistor devices, but adequate design distance between the contact and sidewall spacer to minimize yield fallout.
A second concern to the manufacturer is the cost associated with pattering levels in the manufacturing process. With state-of-the-art transistor gate lengths targeting about 100 nm, each photolithographic mask using minimum geometry may cost as much as $100,000. When the cost of prototype designs is included in the total cost of a semiconductor product, the cost of multiple revisions, each requiring several minimum geometry masks, can be significant.
Consequently, what is needed in the semiconductor arts is a method of manufacturing a transistor device that overcomes the limitations of currently known manufacturing methods.